The present invention is related to priority encoders. More particularly, the present invention is related to the use of circular priority encoders.
Priority encoders are circuits that serve to acknowledge a request having a highest priority (or rank) from among a plurality of requests arriving as active signals to the priority encoder. A request acknowledgment may include enabling a circuit (such as a microprocessor) so that the circuit may execute the task corresponding to the request.
A priority encoder may receive one or a plurality of simultaneous requests on respective request lines (i.e., input lines) assigned with respective ranks, for example from 1 to n. The priority encoder may acknowledge one request at a time through acknowledgment lines. In some encoders, the acknowledgment lines directly correspond to request lines, and the encoder transmits the acknowledged request only on the acknowledgment lines. In some priority encoders, the acknowledgment lines may provide a binary rank of the acknowledged request.
In linear priority encoders, the priorities (or ranks) assigned to the request lines may be distinct. That is, the priorities may be assigned by decreasing order to the ranks of the request lines by starting with a highest rank. Linear encoders may acknowledge the request of the highest rank.
Linear encoders may be implemented as a non-sequential logic circuit, of a carry propagation type, that acknowledges the request of the highest rank after any change in the states of the request lines. The actual delay may depend on the carry propagation time of the circuitry.